Currently, many electronic systems, for example, high voltage Integrated Circuits (ICs), microelectromechanical systems (MEMS), optoelectronics, and other electronic systems require high aspect ratio vias and trenches. Generally, fabrication of electronic components, e.g., vias, trenches, pillars involves etching a semiconductor substrate. Typically, high aspect ratio through silicon vias (TSVs) and trenches are manufactured using a Bosch process that alternates repeatedly between plasma etch and deposition modes. Typically, Bosch process uses repetitions of alternate plasma deposition and etch modes to create a polymer side surface passivation layer while etching the via in a vertical direction.
Currently the polymer passivation layer deposited has an undesirable non-uniform profile. Via fabrication is currently limited with the existing standard nozzle.
Generally, the non-uniformity of the plasma etch and deposition across the wafer leads to variations of the profiles of the electronic components (e.g., pillars, vias, and trenches). That is, any non-uniformity in any of plasma deposition and etch operations can significantly impact not just the via depth uniformity but also profile uniformity across the wafer. Additionally, non-uniformity of the plasma etch and deposition across the wafer can introduce the electronic device defects (e.g., striations, bowing and tapering). As such, the non-uniformity of the plasma etch and deposition across the wafer impacts yield and increases the cost of electronic device manufacturing.